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ds05-10168-4e fujitsu semiconductor data sheet memory cmos 1m 16 bits fast page mode dynamic ram MB81V16160A-60/60l/-70/70l cmos 1,048,576 16 bits fast page mode dynamic ram n description the fujitsu mb81v16160a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 16-bit increments. the mb81v16160a features a ?ast page mode of operation whereby high-speed random access of up to 256-bits of data within the same row can be selected. the mb81v16160a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb81v16160a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb81v16160a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb81v16160a are not critical and all inputs are lvttl compatible. n product line & features parameter mb81v16160a -60 -60l -70 -70l ras access time 60 ns max. 70 ns max. random cycle time 110 ns min. 130 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 324 mw max. 288 mw max. standby current lvttl level 3.6 mw max. 3.6 mw max. 3.6 mw max. 3.6 mw max. cmos level 1.8 mw max. 0.54 mw max. 1.8 mw max. 0.54 mw max. 1,048,576 words 16 bits organization silicon gate, cmos, advanced capacitor cell all input and output are lvttl compatible 4096 refresh cycles every 65.6 ms 1we / 2cas self refresh function early write or oe controlled write capability ras only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance standard and low power versions this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 MB81V16160A-60/60l/-70/70l n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +4.6 v voltage of v cc supply relative to v ss v cc ?.5 to +4.6 v power dissipation pd 1.0 w short circuit output current 50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c (lcc-42p-m01) package and ordering information ?42-pin plastic (400 mil) soj,order as mb81v16160a- pj 50-pin plastic (400 mil) tsop-ii with normal bend leads,order as mb81v16160a- pftn and mb81v16160a- lpftn (low power) plastic soj package plastic tsop packages (fpt-50p-m06) (normal bend)
3 MB81V16160A-60/60l/-70/70l n capacitance (t a = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance, a 0 to a 11 c in1 6pf input capacitance, ras , lcas , ucas , we , oe c in2 6pf input/output capacitance, dq 1 to dq 16 c dq 7pf v cc v ss fig. 1 ? mb81v16160a dynamic ram - block diagram ucas ras we oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 mode control write clock gen clock gen #2 data in buffer data out buffer column decoder clock gen #1 sense ampl & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder refresh address counter row decoder substrate bias gen dq 1 to dq 16 lcas
4 MB81V16160A-60/60l/-70/70l n pin assignments and descriptions designator 42-pin soj (top view) 50-pin tsop (top view) we oe function a 0 to a 11 address inputs row : a 0 to a 11 column : a 0 to a 7 refresh : a 0 to a 11 ras row address strobe lcas lower column address strobe write enable output enable dq 1 to dq 16 data input/output v cc +3.3 volt power supply v ss circuit ground 1 pin index v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dq 1 dq 2 dq 3 dq 4 v cc v ss v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss 21 22 n.c. n.c. a 11 a 10 a 0 a 1 a 2 a 3 v cc dq 12 dq 11 dq 10 dq 9 n.c. a 9 a 8 a 7 a 6 a 5 a 4 we ras lcas ucas oe 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 21 30 v cc dq 1 dq 2 dq 3 dq 4 v cc v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss n.c. dq 12 dq 11 dq 10 dq 9 n.c. 22 29 23 28 24 27 25 26 n.c. a 11 a 10 a 0 a 1 a 2 a 3 v cc n.c. v ss n.c. a 9 a 8 a 7 a 6 a 5 a 4 1 pin index we ras lcas ucas oe ucas upper column address strobe (marking side)
5 MB81V16160A-60/60l/-70/70l n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. since only twelve address bits (a 0 to a 11 ) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, twelve row address bits are input on pins a 0 -through-a 11 and latched with the row address strobe (ras ) then, eight column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min.) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways?n early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas / ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq 1 -dq 8 is strobed by lcas and dq 9 to dq 16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas / ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas / ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are lvttl compatible with a fanout of one ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max.) is satis?d. t cac : from the falling edge of lcas (for dq 1 to dq 8 ) ucas (for dq 9 to dq 16 ) when t rcd is greater than t rcd (max.). t aa : from column address input when t rad is greater than t rad (max.). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . the data remains valid until either lcas / ucas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 256 16-bits can be accessed and, when multiple mb81v16160as are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 3.0 3.3 3.6 v 0 c to +70 c v ss 000 input high voltage, all inputs *1 v ih 2.0 v cc +0.3 v input low voltage, all inputs* *1 v il ?.3 0.8 v
6 MB81V16160A-60/60l/-70/70l n dc characteristics (at recommended operating conditions unless otherwise noted) note 3 parameter notes symbol conditions value unit min. typ. max. std power low power output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = +2.0 ma 0.4 0.4 input leakage current (any input) i i(l) 0 v v in 3.6 v; 3.0 v v cc 3.6 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 10 m a output leakage current i do(l) 0 v v out 3.6 v; data out disabled ?0 10 10 operating current (average power supply current) *2 mb81v16160a -60/60l i cc1 ras & lcas , ucas cycling; t rc = min. 90 90 ma mb81v16160a -70/70l 80 80 standby current (power supply current) ttl level i cc2 ras = lcas , ucas = v ih 1.0 1.0 ma cmos level ras = lcas , ucas 3 v cc ?.2 v 500 150 m a refresh current#1 (average power supply current) *2 mb81v16160a -60/60l i cc3 lcas , ucas = v ih , ras cycling; t rc = min. 90 90 ma mb81v16160a -70/70l 80 80 fast page mode current *2 mb81v16160a -60/60l i cc4 ras = v il , lcas , ucas cycling; t pc = min. 90 90 ma mb81v16160a -70/70l 80 80 refresh current#2 (average power supply current) *2 mb81v16160a -60/60l i cc5 ras cycling; cas -before-ras ; t rc = min. 90 90 ma mb81v16160a -70/70l 80 80 battery backup current (average power supply current) *2 mb81v16160a -60/70 i cc6 ras cycling; cas -before-ras ; t rc = 16 m s t ras = min. to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 800 m a mb81v16160a -60l/70l ras cycling; cas -before-ras ; t rc = 32 m s t ras = min. to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 300 refresh current#3 (average power supply current) mb81v16160a -60/60l i cc9 ras = v il , cas = v il self refresh; 800 250 m a mb81v16160a -70/70l
7 MB81V16160A-60/60l/-70/70l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol MB81V16160A-60/ 60l mb81v16160a-70/ 70l unit min. max. min. max. 1 time between refresh std power t ref 65.6 65.6 ms low power 128 128 2 random read/write cycle time t rc 110 130 ns 3 read-modify-write cycle time t rwc 150 174 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?7ns 6 column address access time *8,9 t aa ?0?5ns 7 output hold time t oh 3?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time *10 t off ?5?7ns 10 transition time t t 350350ns 11 ras precharge time t rp 40?0ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 15?7ns 14 cas to ras precharge time t crp 0?ns 15 ras to cas delay time *11,12 t rcd 20 45 20 53 ns 16 cas pulse width t cas 15?7ns 17 cas hold time t csh 60?0ns 18 cas precharge time (normal) *19 t cpn 10?0ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 10?0ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 15?5ns 23 column address hold time from ras t ar 35?5ns 24 ras to column address delay time *13 t rad 15 30 15 35 ns 25 column address to ras lead time t ral 30?5ns 26 column address to cas lead time t cal 30?5ns 27 read command and set up time t rcs 0?ns 28 read command hold time referenced to ras *14 t rrh 0?ns 29 read command hold time referenced to cas *14 t rch 0?ns 30 write command set up time *15 t wcs 0?ns
8 MB81V16160A-60/60l/-70/70l (continued) no. parameter notes symbol MB81V16160A-60/ 60l mb81v16160a-70/ 70l unit min. max. min. max. 31 write command hold time t wch 15?5ns 32 write hold time from ras t wcr 35?5ns 33 we pulse width t wp 15?5ns 34 write command to ras lead time t rwl 15?7ns 35 write command to cas lead time t cwl 15?7ns 36 din set up time t ds 0?ns 37 din hold time t dh 15?5ns 38 data hold time from ras t dhr 35?5ns 39 ras to we delay time *20 t rwd 80?2ns 40 cas to we delay time *20 t cwd 35?9ns 41 column address to we delay time *20 t awd 50?7ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before-ras refresh t csr 0?ns 44 cas hold time for cas -before-ras refresh t chr 10?2ns 45 access time from oe *9 t oea ?5?7ns 46 output buffer turn off delay from oe *10 t oez ?5?7ns 47 oe to ras lead time for valid data t oel 10?0ns 48 oe hold time referenced to we *16 t oeh 5?ns 49 oe to data in delay time t oed 15?7ns 50 cas to data in delay time t cdd 15?7ns 51 din to cas delay time *17 t dzc 0?ns 52 din to oe delay time *17 t dzo 0?ns 60 fast page mode ras pulse width t rasp 100000 100000 ns 61 fast page mode read/write cycle time t pc 40?5ns 62 fast page mode read-modify-write cycle time t prwc 80?9ns 63 access time from cas precharge *9,18 t cpa ?5?0ns 64 fast page mode cas precharge time t cp 10?0ns 65 fast page mode ras hold time from cas precharge t rhcp 35?0ns 66 fast page mode cas precharge to we delay time t cpwd 55?2ns
9 MB81V16160A-60/60l/-70/70l notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il ucas =v ih , lcas =v ih and v il > ?.3v. i cc1 , i cc3 i cc4 and i cc5 are speci?d at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3v. i cc6 is measured on condition that all address signals are ?ed steady state. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 5 ns. *5. input voltage levels are 0v and 3.0v, and input reference levels are v ih (min) and v il (max) for measuring timing of input signals. also, the transition time (t t ) is measured between v ih (min) and v il (max). the output reference levels are v oh =2.0v and v ol =0.8v. *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to one ttl load and 100pf. *10. t off and t oez are speci?d that output buffer change to high impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min) + 2t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satis?d for a read cycle. *15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satis?d. *18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs > t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state through out the entire cycle. if t cwd > t cwd (min), t rwd > t rwd (min), and t awd > t awd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations.
10 MB81V16160A-60/60l/-70/70l n functional truth table x : ? or ? * : it is impossible in fast page mode. operation mode clock input address input input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes cas -before- ras refresh cycle l l l x x high-z high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l l h l h l l h ? x l valid high-z valid high-z valid valid yes previous data is kept 60ns version fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rad (ns) t cp (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad t rac (ns) t cpa (ns) 60 40 100 80 120 20 060 40 100 80 70ns version 60ns version 60 50 80 70 90 20 040 30 60 50 70ns version 40 30 60 50 70 10 030 20 50 40 60ns version 70ns version
11 MB81V16160A-60/60l/-70/70l t rcs t rc t ras t ar t rp t cdd t rcd t crp t asr t rah t asc t cah t oel t rch t rrh t dzc t oea t oez t dzo t on t oed t oh t off t rad row add column add t ral t cal t aa t cac t rac high-z high-z t oh t csh t rsh t cas t on description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. lcas controls the input/output data on dq1-dq8 pins, ucas controls one on dq8-dq16 pins. the access time is determined by ras(t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: f t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. fig. 5 ? read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol lcas or ucas we dq (output) a 0 to a 11 v ih v il dq (input) v ih v il oe ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
12 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rc t ras t rp t csh t rcd t crp t cas t asr t rah t asc t cah t wcr t wcs t wch t dh t ds t rsh t ar t dhr description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be implemented in either of three ways ?early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. fig. 6 ? early write cycle (oe = ? or ?? column add row add high-z valid data in ras v ih v il v ih v il v ih v il v ih v il v oh v ol lcas or ucas we dq (output) a 0 to a 11 v ih v il dq (input)
13 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rc t ras t rcd t crp t asr t cah t rcs t dzc invalid data t rp t asc t rah t cwl t wp t ds t dh t oed t dzo t oeh t oez t wch t rwl t on t on description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 ? delayed write cycle row add col add high-z valid data i n ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe high-z high-z t ar t rsh t csh t cas
14 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t asc t rwc t ras t rcd t crp t asr t cah t rwl t rcs t rp t rah t cwl t ds t dh t oed t dzo t oeh t rad t cwd t wp t oez t oh t rwd t awd t dzc t cac t rac t aa t on t on t oea fig. 8 ? read-modify-write-cycle description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. valid row high-z high-z high-z add col add valid data i n ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe t ar data
15 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t on t oea t rasp t crp t asr t asc t rcs t rhcp t rp t rcd t cas t rsh t pc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cpa t dzc t dzc t ach t ar t cah t rah t asc t rrh t cah t asc t rch t cdd valid data t dzo t oh t dzo t on t oh t cac t aa t oez t oea t oed t oed t oh t oh t rad t off t csh t ral t oel t off t dzo t cac t oez t aa t rac description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the lastest in occuring. fig. 9 ? fast page mode read cycle t rasp col add row add col add col add high-z high-z ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe high-z high-z
16 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rasp t rp t rsh t pc t rcd t csh t cas t asc t cah t cas t cas t cp t cah t asc t cah t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t rah t ds t dh t ds t dh t ar t wcr t dhr fig. 10 ? fast page mode early write cycle (oe = ? or ?? description the fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq 1 to dq 8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the fast page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. row add high-z col add col add col add valid data valid data valid data ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (output) a 0 to a 11 v oh v ol dq (input) t crp t asr
17 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) description the fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). valid valid col add col add row add high-z fig. 11 ? fast page mode delayed write cycle t rasp t rp t pc t rsh t cas t cas t cp t csh t rcd t crp t asr t rah t ar t asc t cah t asc t cah t cwl t rwl t wch t wp t cwl t wch t rcs t wp t dzc t ds t dh t dh t ds t oed t on t on t oed t oeh t on t dzo t oez t on t oez t oeh ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe invalid data data data
18 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t oed valid data valid valid col add high-z row add fig. 12 ? fast page mode read modify write cycle description during the fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. t rasp t rp t crp t rcd t cwd t rwl t prwc t cp t asc t cah t asc t cah t rad t rah t asr t rcs t awd t cpwd t cwl t rcs t cwl t wp t wp t ds t dh t dh t ds t rwd t dzc t oed t cac t aa t on t on t aa t on t on t rac t dzo t oea t cpa t oeh t oez t oea t oeh t oez ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe t cwd t cac col add
19 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rc t ras t rpc t cpn t csr t chr t rp t off t oh t rc t rp t asr t rpc t rah t crp t oh t crp t ras t off lcas or ucas lcas or ucas fig. 13 ? ras -only refresh (we = oe = ? or ?? fig. 14 ? cas -before-ras refresh (addresses = we = oe = ? or ?? v ih v il ras v ih v il v ih v il v oh v ol a 0 to a 11 v ih v il v oh v ol v ih v il ras dq (output) row address description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4096 row addresses every 65.6-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras. during ras -only refresh, dq pins are kept in a high-impedance state. description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. dq (output) high-z high-z
20 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) t rc t rp t chr t rc t rs t ras t rp t oel t rsh t rad t rah t asc t cah t rcs t rrh t cac t dzc t cdd t dzo t oea t oed t oez t crp t asr t oh t off t on t rcd t ral t ar t aa t rac high-z fig. 15 ? hidden refresh cycle row address description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. high-z column address valid data out ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe
21 MB81V16160A-60/60l/-70/70l t crp t rp t cp t rcs t fcah t asc valid data t cwl t wp t rcd t frsh t rwl t fcwd t dh t ds t dzc t oed t on t oea t dzo t oez t oeh t fcac t fcas lcas or ucas fig. 16 ? cas -before-ras refresh counter test cycle parameter unit min. max. ns no. min. max. 55 50 (at recommended operating conditions unless otherwise noted.) symbol 35 ns 35 92 93 94 77 ns 70 99 ns 90 99 ns 90 MB81V16160A-60/60l mb81v16160a-70/70l access time from cas column address hold time cas to we delay time cas pulse width ras hold time note: assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras a 0 to a 11 v ih v il v ih v il v ih v il v oh v ol v ih v il we dq (input) oe 91 90 t fcac t fcah t fcwd t fcas t frsh column addresses description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a0 through a11 are de?ed by the on-chip refresh counter. column addresses: bits a0 through a7 are de?ed by latching levels on a0-a7 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 4096 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 4096 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) high-z high-z high-z valid data in ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
22 MB81V16160A-60/60l/-70/70l ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) high-z cas fig. 17 ? self refresh cycle (a0 - a11 = we = oe = ? or ?? (at recommended operating conditions unless otherwise noted.) note: assumes self refresh cycle only. parameter unit min. max. no. min. max. 100 100 100 symbol 101 125 110 102 ?0 ?0 m s ns ns ras pulse width ras precharge time cas hold time MB81V16160A-60/60l mb81v16160a-70/70l t rass t rps t chs description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter. if cas goes to ? before ras goes to ? (cbr) and the condition of cas ? and ras ? is kept for term of t rass (more than 100 m s), the device can enter the self refresh cycle. following that, refresh operation is automatically executed at ?ed intervals using internal refresh address counter during ?as =l and ?as =l? exit from self refresh cycle is performed by toggling ras and cas to ? with speci?d t chs min.. in this time, ras must be kept ? with speci?d t rps min. using self refresh mode, data can be retained without external cas signal during system is in standby. restriction for self refresh operation ; for self refresh operation, the notice below must be considered. 1) in the case that distributed cbr refresh are operated between read/write cycles self refresh cycles can be executed without special rule if 4,096 cycles of distributed cbr refresh are executed within t ref max. 2) in the case that burst cbr refresh or distributed/burst /ras only refresh are operated between read/write cycles 4,096 times of burst cbr refresh or 4,096 times of burst /ras only refresh must be executed before and after self refresh cycles. v ih v il ras v ih v il ras v ih v il v oh v ol dq (output) t ns < 4 ms 4,096 burst refresh cycle read/write operation 4,096 burst refresh cycle self refresh operation read/write operation t rass t sn < 4 ms t rass t rps t rpc t chs t csr t cpn t off t oh * read/write operation can be performed non refresh time within t ns or t sn * *
23 MB81V16160A-60/60l/-70/70l n package dimensions 1994 fujitsu limited f50006s-2c-1 42-lead plastic leaded chip carrier (case no.: lcc-42p-m01) dimensions in mm (inches) +0.35 C0.20 +.014 C.008 C.001 +.002 C0.02 +0.05 * lead no 3.40 .134 .008 0.20 (.370.020) 9.400.51 r0.81(.032)typ 0.64(.025)min 2.75(.108)nom details of "a" part 0.81(.032)max. 0.430.10(.017.004) 42 22 21 1 0.10(.004) 2.50(.098)nom (.432.005) 10.970.13 (.400) nom 10.16 index (.050.005) 1.270.13 25.40(1.000)ref 27.300.13(1.075.005) "a" *: this dimension exclude resin protrusion. (each side: 0.15(.006) max)
24 MB81V16160A-60/60l/-70/70l (continued) 50-lead plastic flat package (case no.: fpt-50p-m06) dimensions in mm (inches) 1.150.05(.045.002) (.010) (.006) 0.25 0.15 (.005.002) 0.1250.05 * "a" 0.40(.016)max 0.15(.006)max details of "a" part 0.500.10 (.020.004) 10.760.20 (.424.008) 11.760.20 (.463.008) 10.160.10 (.400.004) 19.20(.756)ref 0.10(.004) 0.80(.031)typ 0.05(.002)min (stand off) 0.13(.005) m 0.300.10 (.012.004) 20.950.10(.825.004) lead no. index 25 15 11 1 26 36 40 50 1994 fujitsu limited f50006s-2c-1 c *: this dimension exclude resin protrusion. (each side: 0.15(.006) max) 1994 fujitsu limited c42001s-2c(w)
25 MB81V16160A-60/60l/-70/70l all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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